Source: CadenceĪ good starting point for any discussion about heterogeneous integration and advanced packaging is an agreed-upon terminology. Following Moore’s Law alone is no longer the best technical and economic path forward. “And by the way, even if it does fit, there is a yield problem. “On the digital side, what you want to fit into your SoC doesn’t fit due to maximum reticle limits,” he said. John Park, product management group director in the Custom IC & PCB Group at Cadence, said design costs for the most advanced chips, including both digital and analog/RF content, can run as much as $1 billion. But the yield benefits also may be minimized when one or more chips/chiplets in a package fail, which is why there has been so much attention on setting standards for integration and interconnects, as well as new and better tools for designing and simulating these increasingly complex systems, and better processes for handling, cleaning, and bonding/debonding Yield is generally higher for smaller chips, which in theory can reduce the overall cost of a multi-chip/multi-chiplet design.That means they either have to be stitched together into a bigger SoC, or they need to be decomposed into one or more functions and integrated in some type of advanced package scheme.

More and different features are required for specific domains and use cases due for competitive reasons, but chips already are bigger than the current reticle allows.That makes scaling an entire SoC uneconomical, because the number of units that need to be sold to recoup NRE costs either must be high enough to justify scaling, or the benefits of scaling need to be considered in the context of a much larger system, such as a processor in a hyperscale data center where the design and manufacturing costs may be offset by the need for fewer servers at significantly lower power. Costs have been rising at each new node since the introduction of finFETs, and they are becoming even more costly with the introduction of gate-all-around FETs and high-NA EUV at 3nm and below.Even the lexicon is changing as engineers try to explain the difference between 3D-ICs, 2.5D, system-in-package, and various types of fan-outs.īehind these changes are several key drivers. And they are interacting with skill sets that in the past existed in another silo, sometimes somewhere else in the world. Nearly every engineer is now working or touching some technology, process, or methodology that is new. The move away from monolithic SoCs to heterogeneous chips and chiplets in a package is accelerating, setting in motion a broad shift in methodologies, collaborations, and design goals that are felt by engineers at every step of the flow, from design through manufacturing.

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